VHDL Program File

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    21:21:38 09/30/2012
-- Design Name:
-- Module Name:    4bitadder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adder is
    Port ( data1 : in  STD_LOGIC_VECTOR (3 downto 0);
           data2 : in  STD_LOGIC_VECTOR (3 downto 0);
              clk : in  STD_LOGIC;
           common : out  STD_LOGIC_VECTOR (1 downto 0);
           to7seg : out  STD_LOGIC_VECTOR (6 downto 0));
end adder;

architecture Behavioral of adder is
    signal summation : STD_LOGIC_VECTOR (4 downto 0) := "00000";
    signal data27seg : STD_LOGIC_VECTOR (3 downto 0) := "0000";
begin

    summation <= ('0'&data1) + ('0'&data2);
   
    common <= "10" when clk = '1' else
                 "01" when clk = '0';

    data27seg <= summation(3 downto 0) when clk = '1' else
                     "000"&summation(4) when clk = '0';

    to7seg <= "1110001" when data27seg = "1111" else
                 "1111001" when data27seg = "1110" else
                 "1011110" when data27seg = "1101" else
                 "0111001" when data27seg = "1100" else
                 "1111100" when data27seg = "1011" else
                 "1110111" when data27seg = "1010" else
                 "1101111" when data27seg = "1001" else
                 "1111111" when data27seg = "1000" else
                 "0000111" when data27seg = "0111" else
                 "1111101" when data27seg = "0110" else
                 "1101101" when data27seg = "0101" else
                 "1100110" when data27seg = "0100" else
                 "1100111" when data27seg = "0011" else
                 "1011011" when data27seg = "0010" else
                 "0000110" when data27seg = "0001" else
                 "0111111";

end Behavioral;